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Method for Very Flat Wafer Polishing

IP.com Disclosure Number: IPCOM000062736D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Luhrs, GH: AUTHOR [+2]

Abstract

A process has been developed for manufacturing thin semiconductor wafers which are mechanically flat. The procedure results in flat polished Si wafers with a flatness maximum of 3 microns while eliminating residual saw marks.

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Method for Very Flat Wafer Polishing

A process has been developed for manufacturing thin semiconductor wafers which are mechanically flat. The procedure results in flat polished Si wafers with a flatness maximum of 3 microns while eliminating residual saw marks.

The process is possible because of specific Si wafer and Si materials etching characteristics. Initially, the surface finish of highly polished and damage-free surfaces does not degrade when etched with KOH solutions. Likewise, the flatness of the surfaces does not degrade with the alkaline etch. Fina chemically- mechanically polished surfaces remain highly specular after etching in KOH.

The procedures followed in the proposed process begin with crystal grinding for diameter control. The crystal is etched to remove grinding damage and fiducial marking is applied for identification and wafer alignment. After slicing edge rounding takes place to reduce edge friability and possible chipping. Lapping is done to eliminate saw marks and this is followed by rough polishing. This step removes mechanical damage on the face of the wafer and generates its basic flatness. The alkaline etching of the wafer in KOH removes edge rounding damage and assures the damage free wafer. A final polishing step completes the process.

Having the etch step fall after the first polish step helps to provide the mechanically flat wafer. If etching were done with acid to remove edge damage, the flatness would be lost. This is not the ca...