Browse Prior Art Database

Method for Processor to Control Its Input Clock Rate

IP.com Disclosure Number: IPCOM000062761D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Hurlimann, DE: AUTHOR [+2]

Abstract

A method is described which allows a processor to double its input clock frequency transparently via control by the processor itself.

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Method for Processor to Control Its Input Clock Rate

A method is described which allows a processor to double its input clock frequency transparently via control by the processor itself.

The method allows a processor to control its input clock rate by driving an external switch from internal programming. The processor that is capable of running at the higher clock rate doubles its own input clock frequency by executing an instruction that is not executed in the slower processor program. Thus, as the faster processor becomes available for use, no change to the existing clock logic is required, but simply a programming change.

The arrangement, shown in Fig. 1, uses an external latch 10 to control an external clock switch 11. It is assumed the power on state of this latch is defined and can be controlled by the processor via software. The initial condition of the output gates the slower clock into the processor clock input. The faster processor software will execute an instruction not executed by the slower processor to drive the output to the opposite state, switching the control to allow the faster cloc be gated into the processor clock input. Fig. 1 uses a single clock source and allows the processor to double its clock frequency. The fast processor executes an instruction to complement the state of the latch, thereby gating the fast clock source into the processor's clock input.

Disclosed anonymously.

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