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Monolithic Memory Cell

IP.com Disclosure Number: IPCOM000072865D
Original Publication Date: 1970-Oct-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Palfi, TL: AUTHOR

Abstract

A basic memory cell and its associated circuitry, to be used in a high speed monolithic memory system, has unique characteristics which allow it to be operated in a reduced power condition until a single cell has been selected, for either write or read operation, by the coincidence of the multidimensional addressing signals. The basic cell is designed to a two-dimensional addressing system. However, with an additional transistor or transistors it can be expanded to three or four dimensions, respectively. The cell contains only three double emitter transistors and four resistors. The circuit operation involves a single positive power supply. However, either a negative or double power supply may be employed.

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Monolithic Memory Cell

A basic memory cell and its associated circuitry, to be used in a high speed monolithic memory system, has unique characteristics which allow it to be operated in a reduced power condition until a single cell has been selected, for either write or read operation, by the coincidence of the multidimensional addressing signals. The basic cell is designed to a two-dimensional addressing system. However, with an additional transistor or transistors it can be expanded to three or four dimensions, respectively. The cell contains only three double emitter transistors and four resistors. The circuit operation involves a single positive power supply. However, either a negative or double power supply may be employed.

The basic cell operates in a bistable mode with the voltage connected to the common point of the collector load resistors R2 and R3. This common point is reduced to a voltage level where stability is maintained. This reduced voltage results in a low current which flows to ground through the common emitter resistor R1. The voltage drop across this resistor is very small so that the emitters of transistors 2 and 3 are slightly above ground. The emitters of transistors 1 and 4 are inactive and the circuit maintains its state.

The X address of the cell brings up the collector voltage of transistor 6 to a positive level determined by the emitter voltage of the X driver circuit. However, the Y driver circuit which is conducting holds the base v...