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Browse Prior Art Database

Tandem I/O System

IP.com Disclosure Number: IPCOM000072890D
Original Publication Date: 1970-Oct-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Hornung, LM: AUTHOR

Abstract

A CPU I/O organization is illustrated in which the devices are hooked in tandem with the highest priority device located adjacent the CPU and the other devices in a descending order of priority, such that the lowest priority device is located at the most remote point from the CPU.

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Tandem I/O System

A CPU I/O organization is illustrated in which the devices are hooked in tandem with the highest priority device located adjacent the CPU and the other devices in a descending order of priority, such that the lowest priority device is located at the most remote point from the CPU.

In such a system, means must be included for providing a positional code which corresponds to the device. As shown, the lines through the devices can be spiralled as they pass through each device. All signals are propagated through a device with one signal being inverted. Considering a logical zero to be at ground level, as a signal is transmitted from the transmitting device lines of a given device, the device may initiate an all zeros code regardless of the otherwise received code by dot OR'ing. Each line is controlled by any device requesting service in this manner. Each line is switched to ground by any device requesting service. The code received by the processor is dependent on the number of devices intervening between the processor and the nearest device requesting service. For a five bit device code bus, ten attached devices may be distinguished as indicated in the table.

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