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Browse Prior Art Database

I/O Interrupt System

IP.com Disclosure Number: IPCOM000072891D
Original Publication Date: 1970-Oct-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Hornung, LM: AUTHOR

Abstract

As shown, a CPU has a channel which includes two interrupt lines. One line is connected to a cycle-steal control in an I/O control while the other line is connected to a subrouting control in the I/O. The device itself determines the type of interrupt which it requests. For instance, if the device is a printer with a format capability for memory access, for printing, the cycle-steal line would be brought up to accomplish a cycle-steal in memory. For more complex operations, such as formatting or justification, the subrouting would be entered into.

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I/O Interrupt System

As shown, a CPU has a channel which includes two interrupt lines. One line is connected to a cycle-steal control in an I/O control while the other line is connected to a subrouting control in the I/O. The device itself determines the type of interrupt which it requests. For instance, if the device is a printer with a format capability for memory access, for printing, the cycle-steal line would be brought up to accomplish a cycle-steal in memory. For more complex operations, such as formatting or justification, the subrouting would be entered into.

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