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Connecting a Selector Channel to a Multiplexor Channel Control Unit

IP.com Disclosure Number: IPCOM000073352D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Olnowich, HT: AUTHOR

Abstract

Information transfer between Select Channel (SC) 10 and Multiplexor Control Unit (CU) 11 involves the following sequences: (1) Initial Selection Sequence (2) Data Transfer Sequence(s) (3) Status Transfer Sequence. This adaptor causes the Operational-In (OP-IN) line 12 to always appear logically enabled to the Select Channel (SC) 10 while at the same time allowing the Multiplexor Control Unit (CU) to drop its Op-In line 13 and raise Request-In (Req-In) line 14 between each of its above listed sequences. The adaptor logic comprises the following: Special Op-In Latch - Latch 15 is set during the initial selection sequence when Status-In rises from CU-11; latch 15 remains set until the Hold-Out signal on line 16 falls.

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Connecting a Selector Channel to a Multiplexor Channel Control Unit

Information transfer between Select Channel (SC) 10 and Multiplexor Control Unit (CU) 11 involves the following sequences: (1) Initial Selection Sequence (2) Data Transfer Sequence(s) (3) Status Transfer Sequence. This adaptor causes the Operational-In (OP-IN) line 12 to always appear logically enabled to the Select Channel (SC) 10 while at the same time allowing the Multiplexor Control Unit (CU) to drop its Op-In line 13 and raise Request-In (Req- In) line 14 between each of its above listed sequences. The adaptor logic comprises the following: Special Op-In Latch - Latch 15 is set during the initial selection sequence when Status-In rises from CU-11; latch 15 remains set until the Hold-Out signal on line 16 falls. SC Op-In Logic - Nand gates 17, 18, & 19 form an OR circuit which gates an up signal on line 20 to SC10 through SCA D&R 21 to Op-In line 12 when either a CU - Op-In signal on line 27 or a SC Op-In signal on line 23 is up. Request-In Service Latch - Latch 24 comprises NAND circuits 25, 26, & 27 connected so that when Latch 15 is set, and CU-11 has raised its Request-In line 14, latch 24 is set by signal on line 28 if a down signal is on Op-In line 13. This causes a signal on line 29 to OR circuit 30 to send a Hold-Out to be sent on line 31 to CU-11 in response to CU's request. Latch 24 is reset by a rise on Address-In on line 32 from CU-11. CU Hold-Out Logic - OR circuit 30 comprises N...