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Browse Prior Art Database

Stuck Track Error Correction

IP.com Disclosure Number: IPCOM000073362D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Christensen, NT: AUTHOR [+2]

Abstract

The bulk storage 10 is comprised of field effect transistor (FET) dynamic shift registers (DSR) in which stored data must be regenerated periodically. Regeneration is accomplished by arranging the cells in recirculating loops and periodically shifting the cells to recirculate the data. For example, each shift register ring may contain 258 bits each, organized in parallel to provide a word of, for example, one or more eight bit bytes. Two bits on each ring are used for "stuck track" detection. That is, word patterns of zeros and ones are written into stuck track positions. As the words containing these bits are read, they are checked for malfunction of the shift register rings.

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Stuck Track Error Correction

The bulk storage 10 is comprised of field effect transistor (FET) dynamic shift registers (DSR) in which stored data must be regenerated periodically. Regeneration is accomplished by arranging the cells in recirculating loops and periodically shifting the cells to recirculate the data. For example, each shift register ring may contain 258 bits each, organized in parallel to provide a word of, for example, one or more eight bit bytes. Two bits on each ring are used for "stuck track" detection. That is, word patterns of zeros and ones are written into stuck track positions. As the words containing these bits are read, they are checked for malfunction of the shift register rings.

The data flow from the bulk storage 10 to a utilization device 20 is as follows. A data word read from the bulk store 10 is stored in sense latches 12. From the sense latches 12 the word is transferred to a data register 14. The data register holds the data while it is operated upon by the error detection logic 16. Proper parity is generated for the word stored in register 14 by means of a parity generator 15 and the resultant word is stored in the I/O buffer 18. Transfers from the I/O buffer 18 to the utilization device 20 are serial by byte over the byte-wide interface line 19. A set of stuck track triggers 22 are provided which record the existence and location of stuck tracks when the data words containing the stuck track pattern are read. Write Operation.

The operation of the control logic is illustrated by means of flow charts B and
C. An input/output operation is commenced by a start I/O instruction from the utilization device. When a write operation is called for, controls load the I/O buffer 18 by transferring four bytes serially across the interface 21. When the I/O buffer is fully loaded, a parity check is performed by the parity check circuit 23. If no parity error occurs, the controls check for all marks, indicating that all bytes of the I/O buffer contain new data to be stored in the bulk store. If all marks are indicated, this is not a partial store and the control logic gates the I/O buffer to the data register 14. Next, the Hamming single error correction-double error detection/error correction code logic 16 generates an error correction code on the words stored in the data register 14. The word is stored along with the error correction bits into the bulk store 10.

If the data flow check for all marks indicated that a partial store has been requested, the data in the a...