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Phase Lock Loop with Variable Delay Line Oscillator

IP.com Disclosure Number: IPCOM000073373D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Laurich, LA: AUTHOR

Abstract

Shown is a system for providing a second order phase lock loop with frequency tracking capability over a wide range of frequencies. The Shown is a system for providing a second order phase lock loop with frequency tracking capability over a wide range of frequencies. The oscillator serves as a source of clocking signals and is made up of a digital variable delay line oscillator having two delay lines 12 and 14 and a shift register 16. The frequency of the delay line oscillator is controlled by the length of time it takes a signal to propagate or circulate through the delay lines and the shift register. The clock signal is passed from the delay line oscillator 10 over line 18 to the phase detector 20.

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Phase Lock Loop with Variable Delay Line Oscillator

Shown is a system for providing a second order phase lock loop with frequency tracking capability over a wide range of frequencies. The Shown is a system for providing a second order phase lock loop with frequency tracking capability over a wide range of frequencies. The oscillator serves as a source of clocking signals and is made up of a digital variable delay line oscillator having two delay lines 12 and 14 and a shift register 16. The frequency of the delay line oscillator is controlled by the length of time it takes a signal to propagate or circulate through the delay lines and the shift register. The clock signal is passed from the delay line oscillator 10 over line 18 to the phase detector 20.

Phase detector 20 compares an input data signal with the clock signal and generates an error signal indicating the phase difference between the clock and data signals. This error signal is used to provide phase and frequency correction to the clock signal.

The error signal is applied over line 22 to the shift register 16 to obtain the phase correction. The phase correction is achieved by causing the shift register 16 to shift a number of times proportional to the size or duration of the error signal from the phase detector 20.

Frequency correction is accomplished by permitting the error signal from phase detector 20 to gate pulses from a master oscillator 24 into shift registers 26 and 28. Shift register 26 is effec...