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Phase Lock Loop with Delay Line Oscillator

IP.com Disclosure Number: IPCOM000073374D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Laurich, LA: AUTHOR [+3]

Abstract

The function of the system shown is to provide a second order phase lock loop for tracking data over a wide range of frequency. The delay line oscillator 10 has a frequency dependent upon the length of time it takes the signal to recirculate in the delay line loop. The clock signal from the delay line oscillator is applied to a counter 12. At the beginning of a period of oscillation, counter 12 is reset to zero and begins to count. Subsequently (possibly simultaneously if synchronized), the input data signal will trigger a set of latches 14 to sample the count from counter 12. This count from counter 12 which is stored in latches 14 will then represent the error or lack of synchronism between the data signal and the clock signal.

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Phase Lock Loop with Delay Line Oscillator

The function of the system shown is to provide a second order phase lock loop for tracking data over a wide range of frequency. The delay line oscillator 10 has a frequency dependent upon the length of time it takes the signal to recirculate in the delay line loop. The clock signal from the delay line oscillator is applied to a counter 12. At the beginning of a period of oscillation, counter 12 is reset to zero and begins to count. Subsequently (possibly simultaneously if synchronized), the input data signal will trigger a set of latches 14 to sample the count from counter 12. This count from counter 12 which is stored in latches 14 will then represent the error or lack of synchronism between the data signal and the clock signal. The count stored in the latches is converted by serializing logic, not shown, in latches 14 into a series of pulses which are outputted over line 16.

The error signal on line 16 is used in two ways. First, the serial pulses are accumulated in an up/down frequency memory 18, and second, the error signal pulses are weighted with a constant factor and applied to a phase correction counter 20. The purpose of the phase correction counter 20 is to advance counter 12 instantaneously a number of counts to bring the data and clock signal back in phase.

To correct for frequency differences between the data signal and the clock signal, the error pulses are accumulated in the up/ down frequency memory 18. T...