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Detecting Phase Error in Phase Encoded Data

IP.com Disclosure Number: IPCOM000073376D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Horowitz, I: AUTHOR [+3]

Abstract

Shown is a phase-error detector to be used in a phase lock loop. The detector detects the phase error between a data signal and a clock signal. The phase lock loop and associated control hardware which generate control signals are not shown.

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Detecting Phase Error in Phase Encoded Data

Shown is a phase-error detector to be used in a phase lock loop. The detector detects the phase error between a data signal and a clock signal. The phase lock loop and associated control hardware which generate control signals are not shown.

The control signals from the phase lock loop are sent to an up/down binary counter 10. Two of the signals tell the counter its start value and stop value, and two of the control signals tell the counter when to count up and when to count down. The function of the up/down counter is to generate a digital sawtooth which is represented as the waveform A in the table. This digital sawtooth approximately counts from zero up to 50 and back down to zero. The maximum count is at the middle of a bit cell, and the zero count is at the beginning and end of the cell.

Phase-error detection is accomplished by monitoring the count in the up/down counter each time a transition in the data waveform is detected. These counts over the length of a bit cell are accumulated in accumulator 22 and the sign and magnitude of the total accumulated count is used as the error signal to control the variable frequency clock and its associated control hardware. The advantage of this detector is that the error signal will direct the variable frequency clock in the proper direction to make a correction, even though the amount of phase error is nearly plus or minus 50% of the bit cell.

In operation, at the beginning of the bit cell, the up/down binary counter 10 is set to start and stop values by controls from the phase lock loop. Complementor 12 is provided to either complement or not complement the count from counter 10, depending upon whether it is desired to add or subtract the count in the counter from the previous accumulated counts. During the first half of a bit cell, the counter 10 is counting up and the complementor does not complement the count output. During the second half of the bit cell, the counter is counting down, and the complementor 12 does complement the count from the counter.

The value from the counter 12 is stored in phase error latches 14 each time a data transition is detected. Pulse shaper 16 converts the data transition into a pulse which is used to set the contents of the complementor into the latches 14. The same pulse out of pulse shaper 16 is delayed by delay 18 and then used to enable the full adder 20.

Full adder 20 adds the counts stored in latches 14 to any Previous accumulated count in the bit cell stored in accumulator 22. At the end of the bit cell, logic 24 will add a plus or minus 50 into the full adder 20, depending upon the sign bit in the accumulator 22. If the sign bit is positive, a negative 50 is added to the value in the accumulator by the full adder 20. If the sign bit is negative, a Positive 50 is added by the full adder to the value in the accumulator. The value in the accumulator is then passed to a variable frequency clock, not show...