Browse Prior Art Database

Buffered Shift Register Memory

IP.com Disclosure Number: IPCOM000073383D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Hoffman, WK: AUTHOR [+2]

Abstract

Rapid access to information stored in a memory consisting of a plurality of recirculating shift registers is obtained with this buffer shift register scheme. A plurality o~ recirculating memory shift registers 10 are connected to a buffer shift register 12 by a plurality of input/output (I/O) circuits 14. A clock 16 is used to control both the memory shift registers and the buffer shift register. In operation, data enters the memory by serial entry into buffer shift register 12, then parallel input of one bit of each word of the data to the memory shift registers 10 through I/O circuits 14. For reading out, the data enters buffer shift register 12 in parallel from memory shift registers 10, then is read out serially from buffer shift register 12.

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Buffered Shift Register Memory

Rapid access to information stored in a memory consisting of a plurality of recirculating shift registers is obtained with this buffer shift register scheme. A plurality o~ recirculating memory shift registers 10 are connected to a buffer shift register 12 by a plurality of input/output (I/O) circuits 14. A clock 16 is used to control both the memory shift registers and the buffer shift register. In operation, data enters the memory by serial entry into buffer shift register 12, then parallel input of one bit of each word of the data to the memory shift registers 10 through I/O circuits 14.

For reading out, the data enters buffer shift register 12 in parallel from memory shift registers 10, then is read out serially from buffer shift register 12. Use of a four phase shifting control for memory shift registers 10 and a two phase shifting control from buffer shift register 12 from clock 16 means that movement of information into and out of buffer shift register 12 may be twice as rapid as movement of information within memory shift registers 10. In MOS technology, this hierarchical shift register memory arrangement allows a very efficient integrated circuit chip layout to give a large number of storage bits in a single integrated circuit chip.

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