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Redundancy Scheme for Shift Register Memory

IP.com Disclosure Number: IPCOM000073384D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hoffman, WK: AUTHOR

Abstract

This redundancy scheme is adapted for use on chip with an integrated circuit memory having a plurality of recirculating memory shift registers 10 coupled to a buffer shift register 12, to allow parallel read out of data from the memory shift registers into the buffer shift register, then serial read out of the data from the buffer shift register 12. A reconfiguring shift register 14, driven synchronously with buffer shift register 12 by clock 16, is provided for storage of information identifying a memory shift register 10 which is defective. Error input 18, coupled to reconfiguring shift register 14, enters the information identifying a defective memory shift register 10.

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Redundancy Scheme for Shift Register Memory

This redundancy scheme is adapted for use on chip with an integrated circuit memory having a plurality of recirculating memory shift registers 10 coupled to a buffer shift register 12, to allow parallel read out of data from the memory shift registers into the buffer shift register, then serial read out of the data from the buffer shift register 12. A reconfiguring shift register 14, driven synchronously with buffer shift register 12 by clock 16, is provided for storage of information identifying a memory shift register 10 which is defective. Error input 18, coupled to reconfiguring shift register 14, enters the information identifying a defective memory shift register 10. Such information is commonly obtained by the "stuck track" technique, in which the presence of a defective memory bit in one of the memory shift registers 10 is detected by a continuous stream of 0's or 1's from the defective memory shift register. Control for the error detection routine is located off chip, such as in a control unit for the memory.

In operation, when reconfiguring shift register 14 presents information at its output 20 indicating a defective memory shift register 10, this disables input/output (I/O) circuit 22, which would otherwise either access information to the defective memory shift register or read out defective information from it. Simultaneously, the information from reconfiguring shift register 14 actuates I/O circuit 24, co...