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Programmable Word Generator

IP.com Disclosure Number: IPCOM000073406D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR [+2]

Abstract

This circuit is directed toward a programmable word generator which comprises an input 10, loading logic 11, twelve recirculating shift registers 12, clocking logic 13, output 14 and display 20. The shift registers 12 are individually loaded. In a manual mode, 32 input pattern switches 15 provide an input signal to the recirculating registers 12 through a manual loading logic circuit 16 and the loading logic circuits 11. In an automatic mode, the input source 17 which sequentially and simultaneously provides the signal to the loading logic circuits 11 may be a computer. The loading pattern or signal placed in each register 12 remains in the register until it is reloaded.

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Programmable Word Generator

This circuit is directed toward a programmable word generator which comprises an input 10, loading logic 11, twelve recirculating shift registers 12, clocking logic 13, output 14 and display 20. The shift registers 12 are individually loaded. In a manual mode, 32 input pattern switches 15 provide an input signal to the recirculating registers 12 through a manual loading logic circuit 16 and the loading logic circuits 11. In an automatic mode, the input source 17 which sequentially and simultaneously provides the signal to the loading logic circuits 11 may be a computer. The loading pattern or signal placed in each register 12 remains in the register until it is reloaded.

In the block diagram of drawing B, each 32-bit recirculating shift register 12 comprises two 16-bit shift registers 30 and 31 which are paralleled so that the effective output signal 32 has a maximum frequency of up to twice the frequency of the registers 30 and 31. In operation, the sequential bit signal of the data pattern from the output of shift registers 30 and 31 pass through conductors 39 and 40, respectively, and is gated by the AND and OR gates, generally designated 35, so that alternate bits appear at the input of the shift registers 30 and 31. Register 30 processes and recirculates all even-numbered bits and register 31 processes and recirculates all odd-numbered bits. The frequency of the clock 36 is divided in half by J-K flip-flop 37 and formed into two phases with each phase applied to the registers 30 and 31, respectively, thus driving them at one-half of the input clock frequency, whereby the registers shift on alternating clock pulses. The output 32 is derived by alternatingly gating the output of the shift registers at the input clock frequency by the logic circuitry 38. If new data is programmed into the ring by manual source 16 or automatic input source 17, the recirculation path is broken, allowi...