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Redundant Memory Cell and Decoder

IP.com Disclosure Number: IPCOM000073412D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR

Abstract

Semiconductor memories are fabricated on chips and include a plurality of cells, normally situated in a matrix arrangement by rows and columns. Manufacturing yields are often significantly decreased due to a defective cell position which requires an entire memory chip array to be discarded. The present circuits disclose redundant memory cells and decoding circuitry which are substituted, by electrical selection, for the defective cells after manufacturing so that the entire chip need not be discarded. The left portion of the figure discloses decoding circuitry connected to a bit line 10. The bit line 10 is connected to a memory location, not shown, and, for purposes of example, is intended to read or write information from the memory cell in response to an address on the plurality of address lines 14: A = 1, B = 0, C = 0.

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Redundant Memory Cell and Decoder

Semiconductor memories are fabricated on chips and include a plurality of cells, normally situated in a matrix arrangement by rows and columns. Manufacturing yields are often significantly decreased due to a defective cell position which requires an entire memory chip array to be discarded. The present circuits disclose redundant memory cells and decoding circuitry which are substituted, by electrical selection, for the defective cells after manufacturing so that the entire chip need not be discarded. The left portion of the figure discloses decoding circuitry connected to a bit line 10. The bit line 10 is connected to a memory location, not shown, and, for purposes of example, is intended to read or write information from the memory cell in response to an address on the plurality of address lines 14: A = 1, B = 0, C = 0.

In normal operation, charging line 12 is raised to a positive voltage, e.g., +10 volts. The charging line 12 connects to each of the decoders. Two of these decoders, e.g., are illustrated at 16 and 18. The 10 volt supply is applied to the gate terminals of each of the bit select FET transistor devices shown at 20 via diode D1, for example. During normal operation lines 24 and 26 are normally kept at ground potential and thus the gating circuits 21 are off. Accordingly, in all the unselected decoders the gate voltage on the bit select transistor 20 is discharged to ground via one of the diodes D2, D3, or D4. However, in the single selected decoder the address signals on address lines 14 are effective to backbias all the diodes D2, D3, D4, such that no discharge path exists from the gate terminal of the bit select transistor 20. In this manner, information is accessed into the memory cell connected to selected bit lines 10 through its associated transistor 20.

Now it is assumed that after manufacturing, it is determined that the memory cell connected to the decoder 16 is defective. In order that it is not necessary to discard the entire memory chip, a redundant memory cell, not shown, is connected to line 30 and a redundant decoding circuit 32 is substituted for decoder 16. With no defective memory cells on the original chip, the redundant memory cell is virtually out of the circuit because diode D6 is negatively poled so as to prevent the charging positive voltage on line 12 from reaching the gate of spare FET bit select transistor 40. In order to remove or disable a decoder and its associated memory cell, e.g., decoder 16, diode D1 is burned out in the following manner. First, line 24 is raised to approximately 10 volts and the address signals for that particular decoder are applied to the plurality of address lines 14. Also, line 12 is raised to a charging or select voltage of +10 volts. This application of signals is operative to turn on its associated bit select transistor 20 and its associated FET transistor F1 whose gate is connected to line 41. During normal operation the s...