Browse Prior Art Database

Large Scale Integration

IP.com Disclosure Number: IPCOM000073413D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR

Abstract

A large scale integrated circuit memory is shown which is functionally operable in accordance with desired known chip circuit characteristics, such as, address lines, chip selection circuitry, and output sensing circuitry. However, rather than mounting a plurality of separate chips on a single surface, a plurality of functionally equivalent chips 12 are integrally formed on a single semiconductor wafer 10. During manufacturing, all chips 12 are connected in parallel by a plurality of conventional deposited metallurgical interconnection lines 14. Although chips in the conventional sense are separate members, the chips 12 represented in this figure are not separate devices but are formed directly into the semiconductor substrate 10.

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Large Scale Integration

A large scale integrated circuit memory is shown which is functionally operable in accordance with desired known chip circuit characteristics, such as, address lines, chip selection circuitry, and output sensing circuitry. However, rather than mounting a plurality of separate chips on a single surface, a plurality of functionally equivalent chips 12 are integrally formed on a single semiconductor wafer 10. During manufacturing, all chips 12 are connected in parallel by a plurality of conventional deposited metallurgical interconnection lines 14. Although chips in the conventional sense are separate members, the chips 12 represented in this figure are not separate devices but are formed directly into the semiconductor substrate 10.

Each chip 12 on the substrate 10 will have its own bit line and word line decoders, not shown, for each of the sixteen chip memories 12 depicted for accessing its own matrix of storage cells. Access to the plurality of metallurgical lines 14 is obtained by a plurality of terminals 16 interconnecting the plurality of respective land patterns 18.

Each chip possesses its own bit line and word line decoders for selecting a particular cell within a chip memory 12. In addition, it is necessary to select and turn on one or more cells located in one (or more) separate chip 12. The group select signal constituted by binary information is provided to the plurality of terminals 16. In this manner, it is not necessary to selectively interconnect different chips 12 during fabrication, such as, by discretionary wiring techniques in order to personalize the memory according to the user's needs. All the chips 12 can be connected in parallel and the selection of one (or more) chip 12 is performed by an addressing signal; this addressing signal goes to one ele...