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Phase Lock Loop Receiver

IP.com Disclosure Number: IPCOM000073417D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Strickland, GC: AUTHOR

Abstract

This signal detector is responsive to tone burst signals closely spaced in frequency for generating corresponding quadrature signals. A phase comparator is used to provide a voltage varying as the phase difference between an applied tone burst signal and a variable frequency oscillator output (VFO). The VFO, in turn, varies as the phase comparison voltage varies. Consequently, a closely spaced tone burst signal having a 10% frequency difference, when applied to the phase lock loop, exhibits a 50% or greater phase shift difference. The phase comparator-VFO feedback loop network replaces passive narrow band filters.

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Phase Lock Loop Receiver

This signal detector is responsive to tone burst signals closely spaced in frequency for generating corresponding quadrature signals. A phase comparator is used to provide a voltage varying as the phase difference between an applied tone burst signal and a variable frequency oscillator output (VFO). The VFO, in turn, varies as the phase comparison voltage varies. Consequently, a closely spaced tone burst signal having a 10% frequency difference, when applied to the phase lock loop, exhibits a 50% or greater phase shift difference. The phase comparator-VFO feedback loop network replaces passive narrow band filters.

Referring to the figure, when the incoming signal shifts from frequency f(1) to f(2) the error signal at B is reduced in width on the next negative transition as the clock shifts back toward its free running frequency. No pulses occur at B on the following cycles. On the first transition in which the incoming signal is lagging the clock, a pulse from A, is applied to the amplifier through the integrator and causes the variable frequency clock to slow down to frequencies f(2) and to operate at 90 degrees phase leading the incoming signal.

By setting the gain of the amplifier to maintain a 90 degrees lead or lag between the clock and the incoming signal, the greatest immunity to edge jitter of incoming signal is realized.

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