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Browse Prior Art Database

Variable Scanning Scheme

IP.com Disclosure Number: IPCOM000073419D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Larsen, LD: AUTHOR

Abstract

In a usual type of scanning scheme, all attached devices are scanned in order of priorities until one having a set service request indicator is found. This device is then serviced and then the priority list is again scanned from the first position. In this type of scanning, one or several of the highest priority devices may be singly or jointly capable of requiring many consecutive storage cycles and could thus monopolize storage access.

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Variable Scanning Scheme

In a usual type of scanning scheme, all attached devices are scanned in order of priorities until one having a set service request indicator is found. This device is then serviced and then the priority list is again scanned from the first position. In this type of scanning, one or several of the highest priority devices may be singly or jointly capable of requiring many consecutive storage cycles and could thus monopolize storage access.

To prevent such monopolization, the priority control circuits are set up to give one of the devices an alternating priority from first to last on alternate scan cycles. In the drawing, the A blocks are AND-INVERTS in which an all positive input condition generates a negative output and an L block is two A blocks with feedback to form a latch, a BT block is a binary trigger or flip-flop and an 1 is an inverter. When a negative pulse is received on line 1, it resets latch 2 whose output 3 drops to set latch 4 and reset latches 5, 6, 7 and 8. This pulse on line 1 also changes the state of trigger 9.

In one state of trigger 9, its output on line 10 is negative and its output on line 11 is positive. In the second state of trigger 9, these output voltage levels are reversed.

With line 10 negative, the output of A block 12 is held positive, but the output line 3 is negative making the output of A block 13 positive to allow latch 5 to remain reset. The voltage drop on output line 14 of latch 5 acts in A block 15 to enable latch 6 to remain reset and similarly, each further latch 7 and 8 can stay reset.

This is the initial state of the logic. The next occurrence is a negative transition of line 20, which sets latch 2 causing latch output line 3 to go positive. This conditions the A block 13 whose output goes negative. The negative going output of A block 13 does two things at the same time. It deconditions the A block 15 and sets the latch 5 whose output line 14 does not go positive until after the output of A block 13 has dropped. Setting of latch 5 causes the + = SEL = DEV = 2, line 14, to become positive and its line 21 causes latch...