Browse Prior Art Database

Distortion Simulator Circuitry

IP.com Disclosure Number: IPCOM000073435D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Froemke, JW: AUTHOR

Abstract

The circuit simulates data set distortion to facilitate on-line testing of a Binary Synchronous Communications Adapter (BSCA), Business Machine Clock feature, internal clock and introduces time distortion into serial binary data for this purpose. Either mark or space levels may be distorted hereby to simulate the received data from a data set, and a bit time may be reduced to about 50% or increased to about 150% of nominal duration.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

Distortion Simulator Circuitry

The circuit simulates data set distortion to facilitate on-line testing of a Binary Synchronous Communications Adapter (BSCA), Business Machine Clock feature, internal clock and introduces time distortion into serial binary data for this purpose. Either mark or space levels may be distorted hereby to simulate the received data from a data set, and a bit time may be reduced to about 50% or increased to about 150% of nominal duration.

The "send data" signal from a data source is converted from an EIA (Electronic Industry Association) voltage level by means of converter circuit 10 which provides both in-phase and out-of-phase outputs. The in-phase output drives single shot 14, and the out-of-phase output drives single shot 12, with a negative transition at the input of either single shot generating a positive output pulse at the output. For any transition of the received data, one of the single shots 12 or 14 generates an input. to OR circuit 16 which converts the signals to drive the clock input of AC trigger 18.

Trigger 18 transfers its input state to its output with each positive transition of the clock input, and there is an inversion of voltage level between the input and output terminals of trigger 18. Converter circuit 20 then converts the voltage level to an EIA voltage level, and the output of converter 20 is used to simulate the "receive data" signal from the data set. The time-out (tp) periods of single shots 12 and 14 are a...