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Random Access Memory

IP.com Disclosure Number: IPCOM000073453D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Zeheb, D: AUTHOR

Abstract

In this multiword random access memory, each memory word comprises a plurality of distinct addressable sections or bytes. Address register 1 is divided in two portions. One stores the conventional X-Y address and the other stores the byte address. Address decoder 2 serves the function of producing X and Y address line select. Boundary decoder 3 receives and decodes a byte address from register 1 and determines the particular byte location at which a given data word is to begin. Outputs of decoders 2 and 3 pass into rotation circuitry block 4 and provide controls to allow the addressing of a given data word stored in memory. This has up to M addressable bytes in which the data word can be addressed beginning on any byte of a memory word. An accessed data word can overlap a memory word boundary into an adjacent memory word.

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Random Access Memory

In this multiword random access memory, each memory word comprises a plurality of distinct addressable sections or bytes. Address register 1 is divided in two portions. One stores the conventional X-Y address and the other stores the byte address. Address decoder 2 serves the function of producing X and Y address line select. Boundary decoder 3 receives and decodes a byte address from register 1 and determines the particular byte location at which a given data word is to begin. Outputs of decoders 2 and 3 pass into rotation circuitry block 4 and provide controls to allow the addressing of a given data word stored in memory. This has up to M addressable bytes in which the data word can be addressed beginning on any byte of a memory word. An accessed data word can overlap a memory word boundary into an adjacent memory word.

Memory 5 is broken up into a plurality of sections A...D. Word drive lines and rotation decoding circuitry is provided so the proper drive lines in each section and at the proper address are in a single memory access cycle even though the specific sections being accessed are in adjacent memory word.

The output of memory 5 is fed through sense circuitry 6 and then directed to memory data register 7 from which the result can be utilized as desired by the system.

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