Browse Prior Art Database

Metallization and Passivation Structures on Semiconductor Devices

IP.com Disclosure Number: IPCOM000073463D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Mullaney, RC: AUTHOR

Abstract

This process comprises selectively etching silicon to expose the underside of metal stripes, terminals, contact holes, oxide interfaces and other elements of semiconductor chips and wafers. Known chemical compounds and mixtures attack and react with silicon without significantly attacking other elements found on a semiconductor chip or wafer. A suitable silicon etch solution comprises by volume 15 parts acetic acid, 15 parts hydrofluoric acid and 25 parts nitric acid.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Metallization and Passivation Structures on Semiconductor Devices

This process comprises selectively etching silicon to expose the underside of metal stripes, terminals, contact holes, oxide interfaces and other elements of semiconductor chips and wafers. Known chemical compounds and mixtures attack and react with silicon without significantly attacking other elements found on a semiconductor chip or wafer. A suitable silicon etch solution comprises by volume 15 parts acetic acid, 15 parts hydrofluoric acid and 25 parts nitric acid.

The process comprises suitably mounting a chip or wafer in wax or any appropriate holder with underside upward on which etch solution is selectively added to dissolve the silicon and washing reaction products with water or any suitable solvent.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]