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Determining Instruction Rates of Computer Processors

IP.com Disclosure Number: IPCOM000073469D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Anthony, AL: AUTHOR [+2]

Abstract

An analytic model has been developed to determine the instruction execution rates for computer systems with buffered processors. The model is essentially a queueing model of processors and I/O devices competing for main storage cycles. The analytic techniques employed are a combination of classical queueing theory and empirical relationships of system parameters related to main storage requests. Input parameters, representing the processor instruction mix, the I/O data rates, and the hardware specifications are mapped into the model which accurately tracks a real system.

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Determining Instruction Rates of Computer Processors

An analytic model has been developed to determine the instruction execution rates for computer systems with buffered processors. The model is essentially a queueing model of processors and I/O devices competing for main storage cycles. The analytic techniques employed are a combination of classical queueing theory and empirical relationships of system parameters related to main storage requests. Input parameters, representing the processor instruction mix, the I/O data rates, and the hardware specifications are mapped into the model which accurately tracks a real system.

The model determines the expected processing rate in MIPS (millions of instructions executed per second) for any specified instruction mix and is obtained from: MIPS = 1 over T + U (WQ + ACC) where T = average instruction execution time when all storage access is successfully made from the buffer, U = proportion of main storage references which cause processor delays, WQ = average time spent in the queue for main storage, ACC = weighted average of store and fetch access time. The proportion of main storage references which cause processor delay is: U = A STO over WI + UC LIO + Y - STO over WI where A = ROe/1-RO/ RO = L/MU = main storage utilization L = LP+LIO = main storage arrival rate LP = (MIPS) (Y) = processor storage request rate LIO = A IO over (BPR) (WI) = effect I/O has upon the processor IO = I/O data rate BPR = bytes per storage reference WI = main storage interleaving factor MU = I/MSCT MSCT = main storage cycle time STO = probability that an instruction is a store UC = probability that main storage references (other than store) cause processor delay and Y = number of main storage requests per instruction per storage module Y = (OPIF)(1-BH)+(STO/WI)+(STO)(KSOB)(1-SIB) + (OPIF+STO)(TLU)(1-TIB) where OPIF = number of operand and I-fetches per instruction BH = probability of buffer bits for operand and instruction fetches KSOB = set equal to 1 when operand is always stored in buffer; otherwise set equal to 0 SIB = probability that the store operand is in the buffer TLU = probab...