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Resistorless Memory Cell Array

IP.com Disclosure Number: IPCOM000073487D
Original Publication Date: 1970-Dec-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Davidson, EE: AUTHOR

Abstract

The use of diode D5 allows this storage cell to operate without a resistive load. Assuming the cell is in the 0 state, it can be placed into the 1 state by raising the Word Write line and lowering the Bit/Sense line simultaneously. This causes current to flow through the path consisting of D5, D3, and P2-N3. When P2-N3 is forward biased, the right-hand SCR turns on. The Word Write line is then returned to its lower state, causing the left-hand SCR to turn on since the P1-N1 junction is already on. Thereafter returning the Bit/Sense line to its high state turns off the right hand SCR leaving the cell in a very low power standby state. Writing a 0 is simply accomplished by raising the Word Write line without pulling down the Bit/Sense line.

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Resistorless Memory Cell Array

The use of diode D5 allows this storage cell to operate without a resistive load. Assuming the cell is in the 0 state, it can be placed into the 1 state by raising the Word Write line and lowering the Bit/Sense line simultaneously. This causes current to flow through the path consisting of D5, D3, and P2-N3. When P2-N3 is forward biased, the right-hand SCR turns on. The Word Write line is then returned to its lower state, causing the left-hand SCR to turn on since the P1-N1 junction is already on. Thereafter returning the Bit/Sense line to its high state turns off the right hand SCR leaving the cell in a very low power standby state. Writing a 0 is simply accomplished by raising the Word Write line without pulling down the Bit/Sense line. This places too low a voltage across the cell for it to be in the 1 state causing it to switch to the 0 state. The half-select threshold is provided by the forward drops of D5, D3, P2-N3 VC2 and the reverse current of D4. It is to be noted that during writing, D5 is forward biased resulting in large charging currents and short time constants for turning the cell on or off.

Reading is achieved by raising the Word Read line until cathode C2 is forward biased. If the cell is in the 1 state, the Bit line is charged through the very low on impedance of the SCR. Enough voltage can be applied to the bit line to directly set a current switch thereby obviating the need for a sense amplifier.

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