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Technique for Communication Between Multiple Logical Macros

IP.com Disclosure Number: IPCOM000073557D
Original Publication Date: 2005-Feb-22
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Abstract

Disclosed is a system for improving communication between logical macros of an application specific integrated circuit (ASIC) or other device that processes data from one function to another. In a system comprised of logical macros there exists a need to define the inter-macro communication such that macros can be developed and tested independently of one another.

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Technique for Communication Between Multiple Logical Macros

Connecting logical macros with a central arbitration and control scheme allows the macros to be efficiently and independently designed and tested. Using this technique, individual macros can be developed and tested using the common inter-macro communication as if other macros were completed, when in fact they may still be under development. This technique improves time to market as the design efforts can be focused on the logical functions of the macros rather than on inter-macro communication.

A central entity that manages arbitration between macros and provides inter-macro connection is employed to provide consistent inter-macro communication protocols and methods. For example, the figure illustrates a central bus controller that connects macros together and provides inter-macro communication. Individual macros would request communication with another macro and when the arbiter grants this request the data is exchanged. As a side benefit, this method also provides some checking of address and byte count and ensures that macro communication maintains the designed format and sequence. The bus controller can be expanded to accommodate as many macros as the target technology will allow. The performance of the bus controller can also be tailored to the needs of the system.

Arbiter

 Address Incrementer

 Byte Count Decrementer

Mux

Data bus

Bus Controller Block Diagram

1

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Macro A

Macro C

  Bus Controlle...