Browse Prior Art Database

Multiple Error Correction

IP.com Disclosure Number: IPCOM000073590D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Bachman, BE: AUTHOR [+2]

Abstract

This circuit automatically corrects multiple errors. When a double error is detected, the word fetched from the memory 10 is read into the error register 12 and the complement of the fetched word is rewritten back into the original memory location. A fetch cycle is then executed on the complement of the fetched word and the word and its complement are compared in an Exclusive OR circuit that will then identify the location of the failing bits. This information is utilized to complement the incorrect bits in the original fetched word in the multiple error unit 16.

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Multiple Error Correction

This circuit automatically corrects multiple errors. When a double error is detected, the word fetched from the memory 10 is read into the error register 12 and the complement of the fetched word is rewritten back into the original memory location. A fetch cycle is then executed on the complement of the fetched word and the word and its complement are compared in an Exclusive OR circuit that will then identify the location of the failing bits. This information is utilized to complement the incorrect bits in the original fetched word in the multiple error unit 16.

The information concerning the failing bits is also stored with the address position of the error. When an error is later detected and there is an address match with the address of the earlier error in the address compare circuit 18, the failing bits in the new error are corrected automatically. If the address position is a commonly used one, the storage of the failing bit data will result in a significant savings in time.

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