Browse Prior Art Database

Binary Decimal Conversion System

IP.com Disclosure Number: IPCOM000073593D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Harper, L: AUTHOR

Abstract

This circuit provides for the conversion of a decimal number into a binary number for ease of storage and processing and reconversion of the number to decimal digits for recording. As indicated on the drawing, a serial memory 1 is provided to retain a desired number of binary numbers which can be selected by energization of a corresponding word select line 2. The bits of the selected word will be shifted out one by one, low order first, by a shift clock 3 and will appear serially on a line 4. Three delay circuits D1, D2 and D3 (which may be AC coupled triggers or master-slave J-K flip flops) store the last three bits read out and are also controlled by clock 3.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Binary Decimal Conversion System

This circuit provides for the conversion of a decimal number into a binary number for ease of storage and processing and reconversion of the number to decimal digits for recording. As indicated on the drawing, a serial memory 1 is provided to retain a desired number of binary numbers which can be selected by energization of a corresponding word select line 2. The bits of the selected word will be shifted out one by one, low order first, by a shift clock 3 and will appear serially on a line 4. Three delay circuits D1, D2 and D3 (which may be AC coupled triggers or master-slave J-K flip flops) store the last three bits read out and are also controlled by clock 3. A full binary adder 5 has one input selectively connected to line 4 or to a line 6 which is the output of delay D3 and its other input connects selectively to a line 7, the output of D1 or to an OR circuit 8. OR circuit 8 enters factors to be added to the number being read from storage 1. These factors may be the binary representation of a decimal digit being entered or a divisor (true or complement) for conversion of the number to a decimal. A sign detector 9 is provided to test the last binary bit of a number and to indicate the number as positive or negative.

In operation, each time a decimal number is to be converted, the corresponding field in memory 1 is read out and is multiplied by a factor of 10. The outputs of 7 and 6 of D1 and D3, respectively, are added in adder...