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Data Reclocker

IP.com Disclosure Number: IPCOM000073604D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Deutsch, H: AUTHOR

Abstract

Serial loop data collection systems have proven extremely effective for collecting data from widespread reporting locations. However, as the serial loop lengthens, jitter increases error rates and restricts the number of stations which can be accommodated on the loop. Dividing the loop into a number of shorter lobes and returning each of the lobes to the central control station, appears to be an effective solution to the jitter problem when coupled with the data reclocking circuit illustrated. A data reclocker is required for each of the lobes into which the loop has been divided. This technique permits an unlimited extension of the loop length insofar as jitter is concerned and the sole limitation on length depends on system and general delay restriction.

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Data Reclocker

Serial loop data collection systems have proven extremely effective for collecting data from widespread reporting locations. However, as the serial loop lengthens, jitter increases error rates and restricts the number of stations which can be accommodated on the loop. Dividing the loop into a number of shorter lobes and returning each of the lobes to the central control station, appears to be an effective solution to the jitter problem when coupled with the data reclocking circuit illustrated. A data reclocker is required for each of the lobes into which the loop has been divided. This technique permits an unlimited extension of the loop length insofar as jitter is concerned and the sole limitation on length depends on system and general delay restriction.

The digital data reclocker uses a complementary set register and clocking to increase the time that an input data bit is available for sampling at a sacrifice of repeating delay. The average time of bit availability is increased by [N - 1] T where N is the number of register positions and T is the bit interval. To attempt to sample the center of the bit availability interval, the average delay is chosen as N/2T. Given an input bit stream, the reclocker will maintain an output bit stream having a bit frequency which is identical to the controlling oscillator frequency as long as the input and output frequencies are such that the bits being received are never ahead or behind the transmitted bit by more than N/2 bits. This is accomplished by sequentially loading a register in a rotating fashion in step with a clock derived from the input data. The first bit is loaded in register position 1 and the second in register position 2. After the Nth bit is loaded in position N, the (N + 1] bit is loaded in position 1 again and so the loading sequence proceeds. After the N/2 position is loaded the first time, the readout starts at position 1 in step with the output clock and rotates in the same manner as the loading rotation. Since readout starts one half cycle out of step with loading, the loading can speed up with respect to the unloading provided a new bit is not loaded into the register before the bit previously recorded therein has been read out. It can also slow down with respect to the unloading provided a new bit is loaded in the register before the previously loaded bit is read a second time.

If the incoming bit stream will never be more than a fraction of a bit ahead or behind where it is expected, the reclocker need only have a two-bit register. Such a reclocker is illustrated with associated timing diagrams and can tolerate a total jitter of + 1/4 bit time assuming an input bit width of one half of the bit...