Browse Prior Art Database

Switching Circuits for Capacitive Correlator

IP.com Disclosure Number: IPCOM000073609D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Gorbatenko, GG: AUTHOR [+2]

Abstract

The analog correlator, view A, is a capacitive storage array using drive lines 10 to weight the sense lines 11 with desired values. The algebraic sum of the driving voltages is zero, and selected ones of the drive lines 10 are coupled to particular sense lines 11 by cross-point capacitors 12. A binary input word on lines 13 controls the closure of summing switches 14 to connect sense lines 11 to amplifier 15 to perform the summation (Image Omitted) where U(I) represents the I-th bit of the input word, and W(IJ) represents the weight coupled to the I-th sense line 11 by the J-th group of lines 10. (Only one such group is shown; sense lines of the remaining groups are coupled to lines 11.) Each group of drive lines 10 corresponds to a stored reference.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Switching Circuits for Capacitive Correlator

The analog correlator, view A, is a capacitive storage array using drive lines 10 to weight the sense lines 11 with desired values. The algebraic sum of the driving voltages is zero, and selected ones of the drive lines 10 are coupled to particular sense lines 11 by cross-point capacitors 12. A binary input word on lines 13 controls the closure of summing switches 14 to connect sense lines 11 to amplifier 15 to perform the summation

(Image Omitted)

where U(I) represents the I-th bit of the input word, and W(IJ) represents the weight coupled to the I-th sense line 11 by the J-th group of lines 10. (Only one such group is shown; sense lines of the remaining groups are coupled to lines
11.) Each group of drive lines 10 corresponds to a stored reference. When the groups are sequentially energized, the input word is correlated with the stored references. Control pulses on line 15a actuate switches 16 to energize each group in turn. Other aspects of the correlator are described in U. S. Patent 3,492,470 to G. G. Gorbatenko.

A bipolar voltage input is applied to drive lines 10 by binary weighted voltage dividers 17A-17E from a positive reference supply +V(REF) and by divider 17F coupled to a negative reference supply -V(REF). Proper operation of the correlator requires exacting dynamic balance between the positive and negative portions of the system. This in turn requires that the closure of switches 16 be simultaneous to within less than one nanosecond. The circuit of view B reduces relative turnon delay to about 0.5 nanosecond between the positive output 18 and the negative output 19. A positive, single-ended logic level at input 15a forces complementary silicon transistors 20 and 21 into saturation, so that their collectors are near zero volts. Germanium diodes 22 and 23 control the depth of saturation. A zero logic level at input 15a forces transistors 20 and 21 to a nonconductive state simultaneously. The positive and negative outputs 18 and 19 then move to +24 volts and -24 volts by the action of resistors 24-27 coupled to the positive and negative 36 volt reference supplies. The collector current is virtually the same in magnitude and identical in time for both transistors, because of th...