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Data Processing Arrangement

IP.com Disclosure Number: IPCOM000073631D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Waddell, JM: AUTHOR

Abstract

Instruction word 10 is obtained from a read-only or writeable control memory. On the left side of the word, it has a split field determined by the numerical value of K. When K is zero, CA and SP address the A and B bus. Also, CA, SP, and CD, as a function of their respective addresses, determine whether a read or write operation is performed in local store 11. When K is equal to 1, CK is gated directly to the A bus as an emit "E" constant to be used by ALU 13 in connection with data signals arriving on the B bus from a selected one of registers 12 or by an external input via AND circuit 14. The B bus signal source is selected by CB. CD designates which addressable register 12 receives a signal from the D bus as an output from ALU 13 or local store 11.

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Data Processing Arrangement

Instruction word 10 is obtained from a read-only or writeable control memory. On the left side of the word, it has a split field determined by the numerical value of K. When K is zero, CA and SP address the A and B bus. Also, CA, SP, and CD, as a function of their respective addresses, determine whether a read or write operation is performed in local store 11. When K is equal to 1, CK is gated directly to the A bus as an emit "E" constant to be used by ALU 13 in connection with data signals arriving on the B bus from a selected one of registers 12 or by an external input via AND circuit 14. The B bus signal source is selected by CB. CD designates which addressable register 12 receives a signal from the D bus as an output from ALU 13 or local store 11. By making the CA, CB, SP, or CD equal to zero, there are no connections respectively to the addressed bus. This means that all zeros are supplied from either the A or B bus to ALU 13 while the result appearing on D bus is lost.

Field OP designates the operations to be performed by ALU 13. It is decoded by decoder 15 as are all the other fields. CS, CH, CL and CX are concerned with addressing control memory and branch operations. The address of the previously executed instruction is kept in ROBAR (read-only-backup-address-register). The current instruction address is kept in ROSAR (read-only-store-address-register). The control memory address has four fields, W, X, H, and L. For facilitating construction of the control memory, fields X, H, and L designate all of the addresses within one memory module. W designates the memory module. In each instruction word, CX is supplied to the X portion of ROSAR for designating the address of the next instruction word. CH and CL are used in conjunction with branch hardware, not shown, for determining H and L. It is permissible in some instructions to unambiguously designate H and L values.

ROSAR is not changeable by an instruction word in which an ALU operation is also performed. For changing the sequence of instructions from one memory module to another, an instruction in OP entitled ":AB to WX" is us...