Browse Prior Art Database

AC Stable Associative Memory Cell

IP.com Disclosure Number: IPCOM000073678D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Dennison, RT: AUTHOR

Abstract

This is an AC stable associative memory cell. The basic cell is shown in drawing A, while the required pulse timing for the operation of the cell is shown in drawing B' The basic cell consists of N-channel FET's, Q1, Q2 and Q4, and P-channel FET Q3. In operation, the cell capacitance C is used to store a positive, zero, or negative charge which corresponds to a "1", a "Phi" (don't care) or a "0", respectively. The cell capacitance C is the effective capacitance designed into the source junction of Q1 and the gates of Q2 and Q3. In order to write information into the cell, the write line and digit line D1 are used. A 1 is written into the cell by bringing the write line positive to turn Q1 on while, at the same time, D1 is brought positive. This charges C to a positive potential, storing a 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

AC Stable Associative Memory Cell

This is an AC stable associative memory cell. The basic cell is shown in drawing A, while the required pulse timing for the operation of the cell is shown in drawing B' The basic cell consists of N-channel FET's, Q1, Q2 and Q4, and P- channel FET Q3. In operation, the cell capacitance C is used to store a positive, zero, or negative charge which corresponds to a "1", a "Phi" (don't care) or a "0", respectively. The cell capacitance C is the effective capacitance designed into the source junction of Q1 and the gates of Q2 and Q3. In order to write information into the cell, the write line and digit line D1 are used. A 1 is written into the cell by bringing the write line positive to turn Q1 on while, at the same time, D1 is brought positive. This charges C to a positive potential, storing a 1. In order to write a Phi (don't care), the D1 line is maintained at ground potential, while the write line is brought positive. This discharges C to a voltage well below the thresholds of Q2 and Q3. Lastly, in order to write a 0, the D1 line is brought negative and the write line is brought positive. This charges C to a negative potential storing a 0.

In order to read the information from the cell, it is necessary to determine the on/off status o~ transistors Q2 and Q3. For this reason, the read line and D1 line are brought to a positive voltage, while D0 is brought to a negative voltage. Current is sensed on the D1 and D0 lines. Assuming that a 1 is stored, the voltage on C is above the threshold of Q2 so that when Q4 turns on a positive current I1 flows through Q2 and Q4 to the grounded word sense line. If a B (don't care) is stored, the voltage on C is nearly zero and both Q2 and Q3 remain off, as Q4 is turned on by the positive read pulse. Thus, no current flows on either the D1 or D0 lines. If a 0 is stored in the cell, the voltage on C is more negative than the threshold of Q3 and, as Q4 is turned on, the negative current I0 flows from the word sense line through Q3 and Q4 to the D0 line.

The search operation is carried out by putting the desired search inform...