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Storage Power Cycling for Data Processing Systems

IP.com Disclosure Number: IPCOM000073680D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Jimerson, LS: AUTHOR [+3]

Abstract

Data from memory 10 is processed through adder 11 in accordance with instructions stored in Main Store 12. Power conservation is achieved without sacrificing computation speed by reading instructions from main store 12 at a faster rate than they are processed. For illustrative purposes, main store 12 is preferably a plated wire storage having multiple instructions contained on a single wire. Faster cycle time of the main store 12 is obtained since time is not required for changing storage address between cycles.

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Storage Power Cycling for Data Processing Systems

Data from memory 10 is processed through adder 11 in accordance with instructions stored in Main Store 12. Power conservation is achieved without sacrificing computation speed by reading instructions from main store 12 at a faster rate than they are processed. For illustrative purposes, main store 12 is preferably a plated wire storage having multiple instructions contained on a single wire. Faster cycle time of the main store 12 is obtained since time is not required for changing storage address between cycles.

The eight instructions resident upon one wire are read sequentially, a half- word at a time, under control of readout counter 13. Readout counter 13 also defines the position in instruction buffer 14 in which the half-word is to be loaded. At the end of the readout, main storage 12 and associated sense amplifiers, sense drivers, address register, parity check and generate circuits, and readout counter are placed in a powered down condition.

Instructions are normally executed sequentially from the instruction buffer 14 under control of the output control counter 15 and the scan control logic 16.

Scan control logic 16 normally causes the main store and associated circuits to be powered up when the last instruction is read from the instruction buffer 14. After the instruction counter 17 is incremented, it is gated into the high-order bit positions of address register 18. The low-order address bits are provide...