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Redundancy Technique for Bad Bit Replacement

IP.com Disclosure Number: IPCOM000073714D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Dunlop, LJ: AUTHOR

Abstract

Defective bit cells having a random distribution within a main memory 10 are rendered ineffective by this scheme which minimizes the proportion of the total storage capacity that must be devoted to corrective action. Each bad bit 11 and 11A in the main memory 10 can be effectively replaced by a good bit 12 and 12A, respectively, in a redundant memory 13. Associated with each word line in main memory 10 is a set of reference bits 14 denoting the number and positions of the bad bits 11 and 11A in the associated main memory word line 15 and the address of the redundancy word line 16 containing the replacement bits 12 and 12A.

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Redundancy Technique for Bad Bit Replacement

Defective bit cells having a random distribution within a main memory 10 are rendered ineffective by this scheme which minimizes the proportion of the total storage capacity that must be devoted to corrective action. Each bad bit 11 and 11A in the main memory 10 can be effectively replaced by a good bit 12 and 12A, respectively, in a redundant memory 13. Associated with each word line in main memory 10 is a set of reference bits 14 denoting the number and positions of the bad bits 11 and 11A in the associated main memory word line 15 and the address of the redundancy word line 16 containing the replacement bits 12 and 12A. During test, the bit address corresponding to each defective bit 11 and 11A in the word line 15 is stored in the reference bits 14, together with the redundancy word address to locate replacement bits 12 and 12A. During data storage operation, information is written into only the good bits in the main memory 10 and a second write operation places information which normally would be in bad bits 11 and 11A in replacement bits 12 and 12A respectively. Thus, bad bits in the main memory 10 are replaced on a one for one basis in the redundancy memory 13. These replacement bits can be located in the same manner in which the original bad bits were located or they may be located sequentially in the redundancy memory 13. At the completion of final test, the bit drivers associated with reference bits 14 are dis...