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Two Level Translation

IP.com Disclosure Number: IPCOM000073729D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Rutchka, A: AUTHOR

Abstract

The total storage capacity of a data processing system includes the actual processor storage as well as all associated auxiliary storage of the system. This total storage capacity is the virtual storage for the system. For purposes of addressing, the virtual storage is divided into a predetermined number of segments each of which, in turn, is divided into a predetermined number of pages with each page consisting of a predetermined number of bytes of data. Dynamic address translation or relocation is the process by which the virtual address of an operand is translated into the physical address of the operand. This is normally accomplished by two levels of translations requiring two additional storage fetch operations.

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Two Level Translation

The total storage capacity of a data processing system includes the actual processor storage as well as all associated auxiliary storage of the system. This total storage capacity is the virtual storage for the system. For purposes of addressing, the virtual storage is divided into a predetermined number of segments each of which, in turn, is divided into a predetermined number of pages with each page consisting of a predetermined number of bytes of data. Dynamic address translation or relocation is the process by which the virtual address of an operand is translated into the physical address of the operand. This is normally accomplished by two levels of translations requiring two additional storage fetch operations. Where the operand is contained in a different or the same page of the same segment from which the next previous operand was obtained, the translation process is accomplished by one level of translation requiring one storage fetch operation.

The virtual address of an operand consists of three parts, namely, a segment field, a page field and a byte field. The segment field corresponds to the high- order bits of the virtual address and defines one of the predetermined segments into which virtual storage is divided. The page field occupies the next high-order bits of the virtual address and specifies one of the predetermined pages within the virtual segment. Finally, the remaining bits of the virtual address identifies one of the predetermined bytes of a given page. Initially, the starting address of a segment table is loaded into the segment table register. Under control of the sequence logic the contents of the segment table register, which represents the origin of the segment table in storage, is added to the segment field of the virtual address to form an address which specifies an entry in the segment table. The first level of translation is completed by issuing a storage fetch request to obtain the contents of that location, which represents the address of the origin of the page table associated with the designated segment...