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Cascade Adder for Multiply Operations

IP.com Disclosure Number: IPCOM000073730D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-22
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Partridge, JE: AUTHOR

Abstract

A cascade adder is provided to add a group of multibit binary numbers. Three bits at a time within a radix position are reduced with conventional carry-save adder logic to a sum and carry into the next higher-order radix position. Each sum and carry thus produced are further combined with other bits, sums and carries in their appropriate radix position three at a time, until all bits and generated sums and carries have been combined and reduced to one or two bits per radix position. These bits are then combined in a conventional carry-propagate adder of sufficient length where carries between stages are allowed to propagate through to provide a correct final sum.

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Cascade Adder for Multiply Operations

A cascade adder is provided to add a group of multibit binary numbers. Three bits at a time within a radix position are reduced with conventional carry- save adder logic to a sum and carry into the next higher-order radix position. Each sum and carry thus produced are further combined with other bits, sums and carries in their appropriate radix position three at a time, until all bits and generated sums and carries have been combined and reduced to one or two bits per radix position. These bits are then combined in a conventional carry- propagate adder of sufficient length where carries between stages are allowed to propagate through to provide a correct final sum.

The cascade adder may be used for high-speed multiply operations eliminating the time needed for successive iterations usually required in conventional multipliers. The following six-bit multiply operation is shown to illustrate the use of the cascade adder:

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The binary bits of the multiplicand are gated to their appropriate radix positions by the binary bits of the multiplier via AND's 1F to 11A corresponding to the positions shown in the example. Three bits at a time within a radix position are reduced with carry-save adders to produce a generated sum at the righthand output and a generated carry at the lefthand output. Thus, for example, CSA-20 responsive to bits 7A, 7B and 7C produces a generated sum output 7 and a generated carry output 6. The g...