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Browse Prior Art Database

Eliminating Thick Oxide in N Channel FET Chips

IP.com Disclosure Number: IPCOM000073735D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+2]

Abstract

This is a method of preventing surface inversion between adjacent FET devices on a monolithic chip. This method comprises passivating the surface of a semiconductor body 10 with a layer of silicon dioxide 11, forming source and drain diffusions 12 and 13, respectively, in selected areas, passivating the gate region 15 of the device between the source 12 and the drain 13 with a silicon nitride layer 17 and diffusing gallium over the entire surface of the body to increase the acceptor surface concentration everywhere, except in the gate region 15 under the silicon nitride layer 17 because the silicon nitride layer 17 prevents the diffusion of gallium. This process thus avoids additional alignment masking and etching steps needed to modify the acceptor surface concentration between adjacent FET devices.

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Eliminating Thick Oxide in N Channel FET Chips

This is a method of preventing surface inversion between adjacent FET devices on a monolithic chip. This method comprises passivating the surface of a semiconductor body 10 with a layer of silicon dioxide 11, forming source and drain diffusions 12 and 13, respectively, in selected areas, passivating the gate region 15 of the device between the source 12 and the drain 13 with a silicon nitride layer 17 and diffusing gallium over the entire surface of the body to increase the acceptor surface concentration everywhere, except in the gate region 15 under the silicon nitride layer 17 because the silicon nitride layer 17 prevents the diffusion of gallium. This process thus avoids additional alignment masking and etching steps needed to modify the acceptor surface concentration between adjacent FET devices.

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