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Browse Prior Art Database

Semiconductor Structure

IP.com Disclosure Number: IPCOM000073743D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Humphreys, CB: AUTHOR

Abstract

A method is described of forming multiple levels of metallization on the surface of a semiconductor chip. Semiconductor chip 10 comprises a number of circuit elements, one of which, an NPN transistor, is shown. All the circuit elements of chip 10 must be interconnected. Beyond a certain number of elements on the same chip, interconnections are done by means of multiple levels of metallization.

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Semiconductor Structure

A method is described of forming multiple levels of metallization on the surface of a semiconductor chip. Semiconductor chip 10 comprises a number of circuit elements, one of which, an NPN transistor, is shown. All the circuit elements of chip 10 must be interconnected. Beyond a certain number of elements on the same chip, interconnections are done by means of multiple levels of metallization.

A passivating coating of silicon oxide 12 and silicon nitride 14 is first deposited on chip 10. Ohmic contact regions 21 and 24 are then formed. Glass layer 29 is applied, and a metallization pattern having the configuration of the first level of metallization is etched in layer 29. Because the etchant used for 29 does not attach layer 14, the metallization pattern is a well-defined trench. Layer 29 fills also the cavities in coatings 12 and 14 at the bottom of which are ohmic contacts 21 and 24. Therefore, the etching process of layer 29 removes also the glass above ohmic contacts in those points of the metallization pattern, where a connection with the circuit elements is desired.

Metallization 25 to 28 is deposited substantially flush with layer 29, for example by calculating the volume of the openings and trenches in layer 29 and passivating layers 12 and 14, then depositing the required amount of metal. The process is repeated for second and third levels of metallization, first depositing a passivating layer 32, 34 on top of the first level of m...