Browse Prior Art Database

Timer for Data Processing Systems

IP.com Disclosure Number: IPCOM000073744D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Halslam, M: AUTHOR [+2]

Abstract

Data processing systems use clock pulses generated by an oscillator every T(1) Mu seconds. These pulses have not normally been used to provide a timer count in which pulses occur every T(2) Mu seconds unless T(2) is an exact multiple of T(1).

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Timer for Data Processing Systems

Data processing systems use clock pulses generated by an oscillator every T(1) Mu seconds. These pulses have not normally been used to provide a timer count in which pulses occur every T(2) Mu seconds unless T(2) is an exact multiple of T(1).

The clock pulses may be used for decrementing the timer count if a compensation is made for the error introduced when the nearest multiple is used, i.e. T(2) = NT(1) + Delta. where N is an integer and

Delta is an error very much less than T2. In the arrangement shown, the Delta error is ignored until it is approximately M times T(1), where M is an integer. An oscillator 4 generates pulses every T1) Mu seconds to increment a counter 3. Counter 3 counts to a value N and provides pulses every T(2) - Delta Mu seconds to a timer counter 2. Counter 3 is reset to zero each time it reaches N. After counter 2 has been decremented a sufficient number of times for the error to have reached M x T(1) counter 3 is reset to -M.

In a particular example it is desired to decrement the timer count every
13.0208 Mu seconds. Oscillator 4 provides system clock pulses every 1 Mu second. Counter is a five bit counter and provides a pulse every 13 Mu seconds to timer counter 2 (N=13). When the count in counter 3 reaches 13, counter 3 is reset to zero (00000). When the decrementing of counter 2 causes bit position 23 to be changed, i.e. every 256th pulse from counter 3, counter 3 is reset to -5 (11011) to compensate...