Browse Prior Art Database

Increased Packing Density of Monolithic Storages

IP.com Disclosure Number: IPCOM000073749D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Veit, R: AUTHOR

Abstract

Known time multiplex methods permit a substantial simplification of the extensive wiring of signal lines and thus, altogether, increase packing densities. In addition to the supply voltage lines, not shown, each storage chip is controlled via two lines, one common clock line A and a single signal line B. To this end, each chip with storage arrays comprises a multiplex gate or selector together with the appertaining array logic, such as address decoder, etc. Synchronously with the selector of the k arrays a selector or gate in the central storage control unit is operated, by means of which the signals for the operation of the storage are serially allocated. As each monolithic semiconductor chip is connected to only two signal lines, the latter may be designed to be extensive and thus be simultaneously used to cool the chips.

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Increased Packing Density of Monolithic Storages

Known time multiplex methods permit a substantial simplification of the extensive wiring of signal lines and thus, altogether, increase packing densities. In addition to the supply voltage lines, not shown, each storage chip is controlled via two lines, one common clock line A and a single signal line B. To this end, each chip with storage arrays comprises a multiplex gate or selector together with the appertaining array logic, such as address decoder, etc. Synchronously with the selector of the k arrays a selector or gate in the central storage control unit is operated, by means of which the signals for the operation of the storage are serially allocated. As each monolithic semiconductor chip is connected to only two signal lines, the latter may be designed to be extensive and thus be simultaneously used to cool the chips. This eliminates the need for an elaborate multilayer module or board design and ensures, in addition to an increased packing density as a result of improved cooling conditions, a higher degree of reliability. The additional logic required per chip is thus more than compensated for.

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