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Diagnostic System for Trapping Circuitry

IP.com Disclosure Number: IPCOM000073752D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Kadner, KM: AUTHOR

Abstract

This circuit relates to testing data processing systems and locates faults in hardware that generates addresses for forced branches or traps. The system locates faults in the trapping circuitry by forcing a branch to a storage address other than that specified in the trap address while preserving the trap address. The address of the forced branch contains successive instructions of a test routine by which the trap address is read out for comparison testing at successive stages until the trap address has been through all the hardware by which it is processed in a normal trap operation.

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Diagnostic System for Trapping Circuitry

This circuit relates to testing data processing systems and locates faults in hardware that generates addresses for forced branches or traps. The system locates faults in the trapping circuitry by forcing a branch to a storage address other than that specified in the trap address while preserving the trap address. The address of the forced branch contains successive instructions of a test routine by which the trap address is read out for comparison testing at successive stages until the trap address has been through all the hardware by which it is processed in a normal trap operation.

This requires only slight additions to the hardware utilized in data processing systems which include trapping. Such systems normally include, in addition to control and operand word storage and processing hardware, equipment for signaling a trap request and for generating an address of a trap routine in storage in accordance with the request and machine conditions, a memory address register to which the generated trap address is provided and which transmits this generated trap address to the storage address registers instead of the next address of the program being executed at the time of the request while preserving, until completion of the trap routine, such next address for return thereto when the trap routine is completed.

The logic required accomplishes what may be described as "trapping" the trap in order to test for failures in the trapping hardware. A requested trap address is generated and processed through the registers as usual, except that the generated trap address is not actually used. Instead, the machine is diverted to another address which is the first address of a test routine for the trapping hardware. This routine reads out for checking purposes the trapping address as originally generated, thereby checking the generating hardware. Similarly such portion of the generated trap address as is further manipulated into and between registers in the normal trapping operation is read out after each manipulation for accuracy check to diagnose any failures in the s...