Browse Prior Art Database

Double Frequency Data/Clock Separator

IP.com Disclosure Number: IPCOM000073758D
Original Publication Date: 1971-Jan-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Schwilk, AF: AUTHOR

Abstract

A circuit for processing double frequency encoded data employs a logic system to separate the data from the clock pulse. A serially transmitted data signal A is received and processed through two channels 10 and 12, the channel 10 separating the data and the channel 12 receiving the separated clock. The input signal is applied to a single-shot multivibrator 14 that responds to the positive-going transitions of A and generates a pulse B, and simultaneously is applied to a single-shot multivibrator 16 that responds to the negative-going transitions of A and produces a pulse C. The data E is passed through the channel 10 by an AND gate 18 coupled to both single shots 14 and 16, and via bistable multivibrator 20 that is normally in the reset condition.

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Double Frequency Data/Clock Separator

A circuit for processing double frequency encoded data employs a logic system to separate the data from the clock pulse. A serially transmitted data signal A is received and processed through two channels 10 and 12, the channel 10 separating the data and the channel 12 receiving the separated clock. The input signal is applied to a single-shot multivibrator 14 that responds to the positive-going transitions of A and generates a pulse B, and simultaneously is applied to a single-shot multivibrator 16 that responds to the negative-going transitions of A and produces a pulse C. The data E is passed through the channel 10 by an AND gate 18 coupled to both single shots 14 and 16, and via bistable multivibrator 20 that is normally in the reset condition. When a binary 1 occurs, the midcell transition (first pulses of the pairs in E) turns the channel on and sets flip-flop 20, and the following transition R resets the flip-flop 20. As a result, a data pulse F output is obtained from the data channel. In the second channel 12, the pulse B or C is passed through the OR gate 22 and applied to a second OR gate 24. In addition, the output of the SS 16 is ANDed with that of 5514 and passed through the AND gate 26 and OR gate 24, and the inverted output H is applied to a flip-flop 28 that provides the clock signal I.

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