Browse Prior Art Database

Pseudo Priority Interrupt System

IP.com Disclosure Number: IPCOM000073783D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Schrage, SL: AUTHOR

Abstract

This system simulates the hardware priority interrupt feature as described in the manual "Data Acquisition Special Features for the IBM System/360 Model 44."

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Pseudo Priority Interrupt System

This system simulates the hardware priority interrupt feature as described in the manual "Data Acquisition Special Features for the IBM System/360 Model
44."

With the optional priority interrupt feature, when a priority interrupt is sensed the hardware automatically stores the old Program Status Word (PSW) and fetches a new PSW from a fixed location-unique for each priority level. Here priority interrupts for software priority levels are generated by a software program, Timer Queue Processor, using the customer engineer instruction DIAGNOSE. This instruction sets priority-interrupt latches as indicated by a general register containing bits set to one corresponding to the priority levels to be set.

The hardware feature determines which priority level will receive control -- higher priorities interrupt lower priorities -- and executes a program attached to the level. When the attached routine has finished, execution on a priority level control is passed to a priority interrupt executive routine. This routine then returns to a lower-priority level via a Load PSW Special (LPSX) and processing continues on the next lowest-priority level. The lower-priority level receiving control will have its priority-request latch set, or have its in-progress latch set meaning it was interrupted previously by a higher-priority level.

To simulate the priority interrupt feature the program is required to simulate the hardware feature. It is desirable t...