Browse Prior Art Database

Data Acquisition and Distribution System

IP.com Disclosure Number: IPCOM000073809D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

This is a binary data communication loop system.

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Data Acquisition and Distribution System

This is a binary data communication loop system.

FIG. A shows a system diagram wherein a data processor 10 controls the reception and transmission of data from loop storage and control unit 12, to terminals 14. Each of the terminals 14 is connected to a wide band communications loop 16 by line adapters 18. The system provides information distribution by a time channel sequence. For example, if a frame of information is transmitted over 256 MHz, then if there are 256 terminals connected on the loop, each terminal would be assigned a 1 MHz bandwidth channel. Thus, every terminal on the loop may receive or transmit information during its channel allocation. The system is not limited to any specific bandwidth since the total frame time may be subdivided into different bandwidth channels. A fixed number of subchannels may be shared by all or any subset of terminals connected to the loop.

FIG. B shows a block diagram of the loop storage and control unit 12. This unit 12 which is connected to data processor 10 controls the reception and transmission of data onto the communications loop 16. Data which are associated with specific terminals, are arranged in storage 20 in a serial fashion as indicated. Thus, terminal 1, for example, would have A0, A1...An placed in storage by means of the address control 22 which determines which locations in storage are to be sequenced for reception or transmission of data onto the shift register 24. Address control 22 determines the transmission of storage data to and from the shift register 24. Data is transmitted or received from register 24 in a serial fashion. That is, each stage of the shift register will hold a bit for a terminal in sequential order. Thus, as bits are transmitted to the line via control clock 26, information will be placed in the appropriate channel in a sequential order; bit A0 in channel time 1, bit B0 in channel time 2, etc. until the end of t...