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Read Only Storage Unit

IP.com Disclosure Number: IPCOM000073831D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Palounek, LR: AUTHOR

Abstract

In the design of logical circuitry, it is desirable to get as many circuit functions as possible on a chip and a major limitation is the limited number of terminal pins available for connections to other modules. The read-only storage module shown requires a small number of pins for a substantial number of functions. In the drawing, 1 is a monolithic storage array shown as having 256 words of 10 bits each with address decoding circuits to select one of the 256 addresses. The decoding circuits are controlled by eight leads 2 from an eight-stage shift register 3 shifted by pulses on a lead 4. The data output from a selected address of storage 1 is passed into a data register 5 and when shift data pulses are applied to a lead 6, the data is shifted to an output lead 7 one bit per pulse.

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Read Only Storage Unit

In the design of logical circuitry, it is desirable to get as many circuit functions as possible on a chip and a major limitation is the limited number of terminal pins available for connections to other modules. The read-only storage module shown requires a small number of pins for a substantial number of functions. In the drawing, 1 is a monolithic storage array shown as having 256 words of 10 bits each with address decoding circuits to select one of the 256 addresses. The decoding circuits are controlled by eight leads 2 from an eight- stage shift register 3 shifted by pulses on a lead 4. The data output from a selected address of storage 1 is passed into a data register 5 and when shift data pulses are applied to a lead 6, the data is shifted to an output lead 7 one bit per pulse.

The shift register 3 is provided with feedback connections to pass the register contents through each possible combination of bits, other than zero, so that each of 255 storage locations may be addressed. As shown, the outputs of the first, fourth, sixth and seventh stages of the register 3 are applied to a four-input gate circuit 8 having an output when the number of inputs is odd and whose output passes through a normally open gate 9 and an OR 10 to be the input of the eighth-stage of register 3. Each shift pulse on line 4 will then shift the register 3 to the next consecutive bit pattern. When it is desired to branch to another address rather than the next...