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Phase Synchronized Clock Generator

IP.com Disclosure Number: IPCOM000073833D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Hippert, RO: AUTHOR

Abstract

This structure is primarily for use in data communications circuits and will generate a clock signal which is in synchronization with a received clock signal.

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Phase Synchronized Clock Generator

This structure is primarily for use in data communications circuits and will generate a clock signal which is in synchronization with a received clock signal.

In the drawing, a data latch 1 receives signals representative of "1's" or "0's" on two lines 2 and 3, respectively. Latch 1 will assume a state corresponding to a received pulse on a line 2 or 3 and will hold that state until a signal is received on the other line. The state of the latch 1 will be set into a trigger 4 by clock pulses on a line 5.

Line 5 is the output of a variable-frequency clock oscillator 6 whose frequency is controlled by a voltage on a lead 7. Clock 6 is synchronized with the received clock pulses on a line 8 by a phase difference detector circuit 9. This detector circuit comprises a 90 degrees phase-shift circuit 10 and an Exclusive OR 11, both receiving the output of clock 6 with the received clock signal on line 8 also connected to Exclusive OR 11. Two AND circuits 12 and 13 each receive the outputs of phase shifter 10 and Exclusive OR 11 with AND 12 also receiving the generated clock signal from oscillator 6 and AND 13 receiving the received clock signal on line 8. The outputs of AND's 12 and 13 are summed up in an amplifier 14 whose output signal, after passing through a low pass filter 15 which passes only the near DC components, appears as the oscillator control voltage on line 7.

In operation, if the two clock circuits on lines 5 and 8 are in...