Browse Prior Art Database

Multistage Switching System

IP.com Disclosure Number: IPCOM000073835D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Cartman, FP: AUTHOR [+2]

Abstract

Illustrated is a 3-stage switching system, with independent and segmented controls organized to effect rapid establishment of connections, as well as simultaneous establishment of plural connections, between central processor units (P) and memory units (M) if a parallel processing system. A storage table associated with each center subswitch defines states of connection of the corresponding central subswitch matrix.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Multistage Switching System

Illustrated is a 3-stage switching system, with independent and segmented controls organized to effect rapid establishment of connections, as well as simultaneous establishment of plural connections, between central processor units (P) and memory units (M) if a parallel processing system. A storage table associated with each center subswitch defines states of connection of the corresponding central subswitch matrix.

The method of establishing connections involves several scanning processes, certain of which may proceed simultaneously. A memory server scanner determines that a requested memory unit is free and assigns stage subswitch has a scanner associated with it; this second scanner establishes the identity of an honored requesting processor associated with that subswitch and initiates a first to second stage link scanner. This link scanner scans each central subswitch storage table to establish an available first to second stage link. A fourth scanning procedure is initiated which determines ultimately whether the central stage identified by the previous scan can be used to connect a requesting processor and requested memory unit.

If it is determined that the identified central stage provides a useful pat (i.e. link: to useful first and third stage subswitch paths), then connections so identified are established by operation of the subswitch crosspoints in the identified first, second and third stages. The corresponding central sub...