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Independent Dual Multiprocessor Programming for Self Test Programs

IP.com Disclosure Number: IPCOM000073858D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Onofrio, RN: AUTHOR

Abstract

Multiprocessor self-test programs can be made to run concurrently using the same copy of the self-test program through the use of a CPU Independent Dual Multiprocessor Programming Technique. This technique is based upon a novel software "flip-flop" scheme formed around the utilization of the IBM System/360 type instruction called Test and Set.

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Independent Dual Multiprocessor Programming for Self Test Programs

Multiprocessor self-test programs can be made to run concurrently using the same copy of the self-test program through the use of a CPU Independent Dual Multiprocessor Programming Technique. This technique is based upon a novel software "flip-flop" scheme formed around the utilization of the IBM System/360 type instruction called Test and Set.

This Test and Set Instruction will address a main storage byte specified; sense whether it was zero or nonzero; then set it to all logical ones. The main storage "busy" indication will not allow any other functional unit to utilize the same location until the busy condition is reset. Therefore, two CPUs could utilize the same Test and Set Instruction at the same time but each could receive different conditions.

The normal approach utilized with the Test and Set Instruction is to "inhibit" the execution of a particular chain of instructions by more than a single CPU at a time in a multiprocessor environment. However, in the scheme presented, the Test and Set Instruction provides a "channeling" function to allow either or both CPUs to perform self-test functions without program time and/or operational restrictions, Executive Program module special interface requirements, and excessive main storage utilization.

The basic software "flip-flop" scheme is depicted on Figure A. Assuming o program module interruptions; such as, supervisor interrupts, the following conclusions can be reached: In single CPU operation, the A & B paths will be on an

alternate basis -- A, B, A, B, etc.

In dual CPU operation, as in single CPU operation, the

paths will be used on an alternate basis. However, no

two CPUs wil...