Browse Prior Art Database

Direct Numeric Control Motion Interface

IP.com Disclosure Number: IPCOM000073861D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Homiak, RL: AUTHOR

Abstract

Operation of the motion interface commences with the initialization of the CPU multiplexor or when a new data word is transmitted. In either case, the control lines WRT SEL and WRT DATA RDY will become true. The signal NOT TOOL RESP ACK will also be true thereby enabling the AND gate 10, indicating data is available. This is then passed through a delay filter 11 (e.g. 5-10 microsecond) which minimizes response to high frequency noise and compensates for any possible skew in the data lines. The thus delayed output (data available) is then gated through AND gate 12 with PERMIT MOTION signal from the controller logic and the Tool Response latch 13 not being set. This is applied as the AC set gate of the REG LOAD FLIP/FLOP which is then set on the leading edge of the LOAD CLOCK on line 15.

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Direct Numeric Control Motion Interface

Operation of the motion interface commences with the initialization of the CPU multiplexor or when a new data word is transmitted. In either case, the control lines WRT SEL and WRT DATA RDY will become true. The signal NOT TOOL RESP ACK will also be true thereby enabling the AND gate 10, indicating data is available. This is then passed through a delay filter 11 (e.g. 5-10 microsecond) which minimizes response to high frequency noise and compensates for any possible skew in the data lines. The thus delayed output (data available) is then gated through AND gate 12 with PERMIT MOTION signal from the controller logic and the Tool Response latch 13 not being set. This is applied as the AC set gate of the REG LOAD FLIP/FLOP which is then set on the leading edge of the LOAD CLOCK on line 15.

The LOAD CLOCK is gated by REG LOAD FLlP/FLOP 14 through AND gate 16 along with PULSE COUNT ZERO and MPX NOT DATA ERR STOP. The latter two of which had been forced to a true condition. This combination produces the MPX REG LOAD pulse which causes the MPX data from CPU on bus 17 to be loaded into the motion and control registers 18 & 19. This load signal occurs essentially on the leading edge of the Load Clock.

The motion and control registers 18 & 19 are checked for both parity and axis command errors by parity check 20 and motion axis data check 21 to assure that both a plus and minus motion command are not simultaneously present on the same axis. If either type of error occurred, it would be detected immediately after the registers 18 & 19 were loaded. If the error was still present at the end of the LOAD CLOCK pulse, the error counter 22 would be incremented. Additionally, the detected error blocks the PULSE C/LOCK, thereby preventing transfer of the register data through motion gate 23 to the controller servos, and alerts the program to the error condition by causing a WRT ALERT interrupt through the MPX channel 17.

On the next LOAD CLOCK pulse, the registers 18 & 19 are reloaded and parity again tested. If still bad, the error counter 22 is again incremented. This sequence continues until either good data is detected or the...