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MOSFET Powering Circuit

IP.com Disclosure Number: IPCOM000073895D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Sonoda, G: AUTHOR

Abstract

The use of capacitor C1 enables the output Vout of this circuit to reach the level of the supply potential +V which would be impossible without the capacitor C1. The input voltage Vin is normally up so that devices Q1 and Q2 are on. This keeps node D below the VT level for device Q3. The device Q3 therefore remains off and the output Vout is zero volts. Under these conditions nodes C and E are biased a little lower than one VT level below the positive power supply potential +V and the capacitors C1 and C2 are both charged to almost +V -VT. Therefore, when the inputs are lowered to the input devices Q1 and Q2 off, node D will begin to rise towards the bias voltage of node C. This turns on device QS which in turn charges the load capacitance C1.

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MOSFET Powering Circuit

The use of capacitor C1 enables the output Vout of this circuit to reach the level of the supply potential +V which would be impossible without the capacitor C1. The input voltage Vin is normally up so that devices Q1 and Q2 are on. This keeps node D below the VT level for device Q3. The device Q3 therefore remains off and the output Vout is zero volts. Under these conditions nodes C and E are biased a little lower than one VT level below the positive power supply potential +V and the capacitors C1 and C2 are both charged to almost +V -VT. Therefore, when the inputs are lowered to the input devices Q1 and Q2 off, node D will begin to rise towards the bias voltage of node C. This turns on device QS which in turn charges the load capacitance C1. As the load capacitance CL charges, node C is forced to rise above its initial value due to the feedback through capacitor C. This allows node C, and therefore node D, to rise permitting the output voltage to rise to the power supply potential +V.

The value of C1 is chosen so that about 80 percent of the output voltage is coupled to node C. The circuit cannot sustain the high-voltage DC levels indefinitely because of leakage currents associated with the capacitive loads.

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