Browse Prior Art Database

MOSFET Storage Chip Bit Line Bias Generator

IP.com Disclosure Number: IPCOM000073896D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Hsieh, JC: AUTHOR [+2]

Abstract

This circuit provides a well regulated, low-potential bias voltage from a more positive supply voltage with low-power dissipation and low-output resistance.

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MOSFET Storage Chip Bit Line Bias Generator

This circuit provides a well regulated, low-potential bias voltage from a more positive supply voltage with low-power dissipation and low-output resistance.

Device Q3 provides the output current while devices Q1 and Q2 set the DC voltage level at the input through the negative feedback path from the output to the gate of device 22. As more current is demanded at the output, the voltage at the output will drop slightly reducing current flow through device Q2 to raise the voltage at node N1 and thereby make device 23 more conductive to compensate for the added current drain. To reduce the power dissipation for the circuit, a positive potential is applied to node N2 and coupled to node N1 by capacitor C during times when an added current drain is anticipated or prescribed.

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