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Insulated Gate Field-Effect Transistor Sense Amplifier Latch

IP.com Disclosure Number: IPCOM000073903D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Surgent, JG: AUTHOR

Abstract

Previous amplifiers for sensing (reading) the data out of an IGFET (insulated gate field-effect transistor) memory cell required that a bipolar transistor sense amplifier be interfaced with an IGFET cell which meant the addition of interface circuitry and an increase in complexity due to the mixing of two technologies. The circuit illustrated in A eliminates these problems by using IGFETs for the sense amplifier as well as the memory cell.

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Insulated Gate Field-Effect Transistor Sense Amplifier Latch

Previous amplifiers for sensing (reading) the data out of an IGFET (insulated gate field-effect transistor) memory cell required that a bipolar transistor sense amplifier be interfaced with an IGFET cell which meant the addition of interface circuitry and an increase in complexity due to the mixing of two technologies. The circuit illustrated in A eliminates these problems by using IGFETs for the sense amplifier as well as the memory cell.

The IGFET Sense Amplifier Latch is designed to latch up with +V at the output 1 when the B0 data line is at a high impedance and is reset by turning ON device 2. Device 3 is operated as a constant current source, as shown in B, by biasing the gate at a constant voltage +VGG in the pinch-off region such that small variations in the drain to source voltage VDS will not change the source current I appreciably. When the sense operation is to take place, the B0 data line is switched into the memory cell by external circuitry, not shown.

The B0 data line becomes either a high impedance line or a low impedance line depending on the presence of a logical "1" or a "0" state in the memory cell. If a 0 or a low impedance exists on the B0 data line, then the line acts as a current sink and the voltage at node 5 is less than the threshold voltage of device
4. When the B0 line switches to the high impedance condition (indicating the presence of a 1 in the memory cell), the current...