Browse Prior Art Database

Three Stage Switching With Preconfigured Center Stage Subswitches

IP.com Disclosure Number: IPCOM000073930D
Original Publication Date: 1971-Feb-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Cartman, FP: AUTHOR [+2]

Abstract

Illustrated is a 3-stage cross-connection switching system with independent and segmented controls. Connections are rapidly established through this system between central processor units (P) and memory units (M) of a parallel processing system. Plural connection requests can be processed simultaneously.

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Three Stage Switching With Preconfigured Center Stage Subswitches

Illustrated is a 3-stage cross-connection switching system with independent and segmented controls. Connections are rapidly established through this system between central processor units (P) and memory units (M) of a parallel processing system. Plural connection requests can be processed simultaneously.

A relatively static storage table associated with each center subswitch defines states of connection or the corresponding central subswitch matrix. In the event of a network malfunction, the table can be modified to provide a new connection topology.

Each processor subswitch has links which provide connections to the center stage subswitches. Center stage subswitches have links and preconfigured crosspoint closures which provide distinct connections to the memory subswitches. Center subswitches may be preconfigured alternately to provide singular or multiple linkage paths between particular processor and memory subswitches.

Drawing A illustrates a system for selectively connecting 16 processors, P(0)- P(15), with 4 memory units, M -M . The center stage subswitches are preconfigured to the indicated connection states by corresponding entries in the above-mentioned storage table. Associated entries are placed in each table and maintained on a long term basis (seconds, minutes, etc.). Connections, when available, are established within nanoseconds of respective processor initiated requests.

Associated with each processor subswitch are link scanners for examining all possible paths to any memory subswitch. Hence the total number of scanners per processor subswitch is the product of the number of center stages and the number of memory subswitches. Accordingly, for processor subswitch #1 (P(0)- P(3)), there would b...